1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device including a power supply circuit generating an internal power supply potential.
2. Description of the Background Art
In recent years, transistor miniaturizing technologies have been remarkably developed so that transistors mounted on a semiconductor chip have dramatically increased in number. This achieves a large capacity of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM), and also achieves a one-chip structure of a memory and a logic circuit. Also, an external power supply ext.Vdd supplied to a chip can be reduced, and thereby a current consumption can be reduced. Owing to this, the device can be employed in a battery-powered instrument.
However, in view of reliability of a transistor, it is difficult to use external power supply potential ext.Vdd as a drive power supply potential of transistors without lowering it, although a low potential is used as external power supply potential ext.Vdd. A further lower potential is required as an internal power supply voltage Vdd. It is also necessary to generate internal potentials such as a substrate potential Vbb for controlling a threshold voltage Vth of the transistor, and a boosted potential (Vpp) for sufficiently increasing the gate potential of the transistor and thereby allowing sufficient transmission of the power supply potential level by the transistor.
Among various potentials which are internally generated, a boosted potential Vpp used in a synchronous DRAM (SDRAM) will now be discussed. The boosted potential Vpp is the highest potential among those used in the chip, and must be determined most carefully in view of reliability of the transistor.
FIG. 20 shows a typical example of an arrangement of a boosted potential generating circuit system and boosted potential power supply lines in the prior art.
Referring to FIG. 20, a semiconductor memory device 860 has a rectangular semiconductor substrate. Memory array banks 862a, 862b, 862c and 862d each having a rectangular form are arranged in positions on the substrate corresponding to the respective corners.
A central region CRS extends along a line connecting midpoints of the opposite short sides of semiconductor substrate together. The device is provided at central region CRS with a Vref generating circuit 834 which generates a reference potential Vrefd forming a reference of boosted potential Vpp, a Vpp level detecting circuit 832 which refers to reference potential Vrefd, and thereby can detect the fact the level on a boosted potential power supply line becomes lower than an desired value, and Vpp pump circuits 836a and 836b which apply the boosted potential to the boosted potential power supply line in accordance with a signal VPLOW activated in accordance with the result of detection.
The boosted potential power supply line has a ring-like form. The boosted potential power supply line includes a portion 866 connected to Vpp pump circuit 836a and Vpp level detecting circuit 832, portions 864a, 864b, 864c and 864d, which are arranged on memory array banks 862a, 862b, 862c and 862d, respectively, and a portion 868 connected to Vpp pump circuit 836b.
The boosted potential power supply line further includes a portion 865 connecting portions 864a and 864c together, and a portion 867 connecting portions 864b and 864d together. Portions 866, 864a, 865, 864c, 868, 864d, 867 and 864b of the boosted potential power supply line are connected in this order to form a ring-like connection around central region CRS.
This boosted potential power supply line in the ring-like form is called a Vpp trunk line. The Vpp trunk line is commonly used by the four memory array banks, and the level on the Vpp trunk line is always monitored by Vpp level detecting circuit 832. Each bank is independently selected and activated.
When the unselected bank is selected, or the selected bank is set to the unselected state, the current is consumed, and the current corresponding to the this current consumption is supplied from the boosted potential power supply line to each bank. Thereby, Vpp level detecting circuit 832 detects lowering of level on the boosted potential power supply line. Signal VPLOW is activated to attain H-level. Thereby, Vpp pump circuits 836a and 836b are activated, and the potential level on the boosted potential power supply line rises.
For stabilizing boosted potential Vpp, it is effective to increase the speed of response of the Vpp level detecting circuit and to prepare a sufficient decouple capacity (not shown). Increase in speed of response of the Vpp level detecting circuit results in increase in current consumption of the Vpp level detecting circuit. During a standby, however, the current consumption with the boosted potential hardly occurs, and therefore the standby current can be reduced by employing another Vpp level detecting circuit dedicated to the standby.
Since boosted potential Vpp is high, a gate area may be restricted due to restrictions on reliability of the device when an MOS capacity is utilized as a capacitor used in a pump circuit. A boosted potential generating Circuit system is designed in consideration of the above.
However, if the raised power supply potential monitored by the Vpp level detecting circuit does not reflect the current consumption with the actual raised power supply potential in the most faithful fashion, even the design of the boosted potential generating circuit system having an optimum performance becomes less significant. In particular, the array structure of, e.g., an SDRAM is formed of a plurality of memory array banks, and the current consumption on the Vpp trunk line may not occur uniformly in a chip including such an array structure. It is now assumed in FIG. 20 that Vpp pump circuits 836a and 836b supply equal currents, when the current is being consumed by activation of memory array banks 862c and 862d. In this case, the voltage drop occurs due to a resistance component of the boosted potential power supply line itself even if Vpp level detecting circuit 832 performs the control to place a desired potential on the boosted potential power supply line. Therefore, the potentials on the portions near memory array banks 862c and 862d may lower slightly below the desired potentials.
However, it is desired to arrange the Vpp level detecting circuit only in one position for avoiding increase in layout area and complication of control.
FIG. 21 shows an example of layout of a conventional power supply circuit.
In a conventional structure shown in FIG. 21, power supply circuits 920 and 930 including Vpp pump circuits, decouple capacities and others occupy an extremely large area. Therefore, these circuits are often arranged in portions of central region CRS near the outer periphery of the chip. As a result, these are often located in the positions remote from consumption portions where boosted potential Vpp is used and thereby the current is actually consumed. Therefore, such a problem arises that interconnection resistances which are present between the consumption portions and power supply circuits 920 and 930 impede smooth supply of currents.